Integrated circuit testing is critical at both the design level to confirm proper operation of a given design and at the manufacturing level for ensuring a given integrated circuit (IC) meets all manufacturing specifications prior to shipment. In response to increasing complexity of ICs and consumer demand for high quality and low failure rate, the integrated circuit manufacturing industry has developed large, complex, and expensive testers for integrated circuits, integrated circuit assemblies, and printed circuit board assemblies for performing these tests. These sophisticated testers require knowledgeable engineers to develop thorough suites of tests that test many aspects of the IC, including continuity testing, functional testing, current testing, etc. As a result, integrated circuit manufacturers typically employ dedicated test engineers to develop these test suites. As a further result, there is typically a high degree of reliability of integrated circuits that pass the tests.
However, once the IC is assembled into a larger system and installed at a customer's site, diagnostic testing of the IC in the face of failures of the larger system can be difficult. For starters, access to the sophisticated testers that can determine whether or not the IC is defective and/or whether and what repairs might be performed to overcome the identified problems is not available without physically removing the IC from the system and sent to a remote test site, for example the manufacturer, for diagnostics. However, even when the IC is tested using a sophisticated tester and using tests designed by the test engineers for manufacturing test of the IC, certain defects may not be recognizable because the circumstances which lead to the defective operation of the system may not be regenerated by the manufacturing tests—in other words, the defective operation of the IC may only be regenerated by operation within the system that the IC is installed in. Furthermore, even when the IC is easily removable, removal of the IC from the system debilitates the system it was removed from for days, which in some circumstances can be quite costly to the customer. Depending on various business-related factors, companies responsible for proper operability of the IC within the system may send field engineers to the customer site for diagnostics, and/or may replace the IC within the customer's system. Both of these solutions can be very costly to one or both of the responsible company and customer in terms of travel costs, engineering time, cost of replacement of the IC, and system down-time. Furthermore, simple replacement of the IC may not provide a solution to the problem if the cause of the problem is a result of a system state that is outside of the IC specifications.
Within the manufacturing test industry, present trends in improving manufacturing testability of integrated circuits include Design for Test (DFT) and Concurrent Test (CCT) techniques. DFT techniques are general design procedures, practices and rules that fit or link circuit testability to the development of manufacturing environments. DFT requires the addition of specialized test hardware on the integrated circuit itself that is independent of the circuitry implementing the intended functionality of the integrated circuit. Traditional DFT techniques include Scan Techniques (for example, using the IEEE 1149.1 Boundary Scan and Joint Test Access Standard (JTAG) protocols), Built In Self Test (BIST), and IDDQ tests.
During testing, the integrated circuit is placed into a test mode that is different from its normal operating mode. When in test mode, test data is routed to the functional blocks under the control of the DFT specialized test hardware rather than from external integrated circuit pads (i.e., the DFT hardware replaces the I/O pins for data/address/control I/O signals). The DFT hardware applies test data to the block under test, and receives return results. Analysis of the result data may be performed by the DFT hardware, or may be output to an external tester device for off-line analysis.
DFT hardware is typically designed to reduce the number of full functional test channels (and therefore physical test probes) required for test access. This is achieved using various techniques. In Scan testing, a scan storage cell is implemented for each input and output of interest of the functional circuit block under test. The scan storage cells are connected together in a serial chain, which is connected at an input to a scan-in port of the integrated circuit and connected at an output a scan-out port of the integrated circuit.
DFT designs typically feature centralized or decentralized Test Access Mechanisms (TAM) through which data passes. In a traditional DFT test, these TAMs receive test data from integrated circuit pins or pads connected directly to tester resources. Test data is loaded into the scan chains via a serial scan load operation, for example using the IEEE 1149.1 Boundary Scan and JTAG protocols, incorporated herein by reference for all that it teaches. The scan storage cells are multiplexed with the data path coming from another functional circuit block or from the integrated circuit I/O pads used during normal operation of the integrated circuit. In this regard, when the integrated circuit is placed in a test mode, data is applied to the inputs and outputs of interest of the functional circuit block under test from respective scan storage cells, and when the integrated circuit is placed in a normal operating mode, data is applied to the inputs and outputs of the functional circuit block under test via the normal data path (typically from an I/O pin or an I/O signal from another functional block on the integrated circuit). In the standard JTAG protocol, data is loaded into the scan chains via a Test Data In (TDI) serial input port, and data is output from the scan chains via a Test Data Out (TDO) serial output port. Accordingly, access to any number of I/O ports within the integrated circuit is made available via only five pads of the integrated circuit. These pads include pads designated for Test Mode Select (TMS) for setting the control operation of the JTAG circuitry, Test Data In (TDI) for inputting data to the scan chains, Test Data Out (TDO) for receiving data output from the scan chains, Test Clock (TCK) for clocking JTAG state machine and the transfer of data within the scan chains, and Test Reset (TRST) for initializing the JTAG state machine and scan chain data to an initial known state.
In the IEEE 1149.1 Boundary Scan and JTAG protocols, data is applied serially to the integrated circuit, and therefore requires more time to execute tests. Accordingly, concurrent testing (CCT) and compression techniques may be implemented to assist in reducing test time. CCT techniques allow independent and concurrent testing (i.e., testing in parallel) of independent functional blocks on the integrated circuit. CCT techniques rely on partitioning the functionality of the overall intended integrated circuit functionality into independently testable functional blocks during the design phase.
Accordingly, it would be desirable to overcome the problems of the prior art described above, by providing an integrated circuit testing technique that reduces the required integrated circuit test pin/pad count, decreases test time, and is economical.